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8 ATA command description
This section defines the software requirements and the format of the commands the Host sends to the
Drive. Commands are issued to the Drive by loading the required registers in the command block with the
supplied parameters, and then writing the command code to the Command Register. There are three classes
of command acceptance, all dependent on the host not issuing commands unless the Drive is not busy (BSY
is ‘0’).
Class 1: Upon receipt of a Class 1 command, the Drive sets BSY within 400ns.
Class 2: Upon receipt of a Class 2 command, the Drive sets BSY within 400ns, sets up the sector
buffer for a write operation, sets DRQ within 700μs, and clears BSY within 400ns of setting DRQ.
Class 3:Upon receipt of a Class 3 command, the Drive sets BSY within 400ns, sets up the sector
buffer for a write operation, sets DRQ within 20ms (assuming no re-assignments), and clears BSY
within 400ns of setting DRQ.
For reasons of back ward compatibility some commands are implemented as ‘no operation’ NOP.
summarizes the Drive command set with the paragraphs that follow describing the individual commands
and the task file for each.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 37 of 76
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